Many of semiconductor device testing apparatuses for measuring the electrical characteristics of semiconductor devices to be tested, i.e. devices under test, by applying a test signal of a predetermined pattern to the devices have a semiconductor device transporting and handling (processing) apparatus (hereinafter referred to as handler) connected thereto for transporting semiconductor devices to a testing or test station where they are brought into electrical contact with sockets of the test head of the testing apparatus, followed by carrying the tested semiconductor devices out of the testing station and sorting them out into conforming (pass) and non-conforming (failure or defective) articles on the basis of the data of the test results.
In the following disclosure the electric or electronic part of the semiconductor device testing apparatus which measures the electrical characteristics of semiconductor devices under test by applying a test signal of a predetermined pattern to the devices is referred to as tester part, and a testing apparatus comprising the tester part and a handler or handlers connected to the tester part is referred to as semiconductor device testing apparatus (as will be referred to as tester hereinafter).
Generally, there are many cases that a tester comprising one tester part and two handlers connected to the tester part is operated as one tester. In such cases, the tester is arranged such that the two handlers are synchronously operated so that semiconductor devices in the two handlers can be tested at the same time. Also, there is often used a tester comprising one tester part and one handler which has two test stations provided therein and the two test stations are synchronously operated so that semiconductor devices in the two test stations can be tested at the same time.
In the following disclosure, for clarity of explanation, the present invention will be described by taking ICs typical of semiconductor devices as an example thereof.
First, one example of the testers of the type to which the present invention is intended to be applied will be described with reference to FIGS. 5 to 7.
FIG. 5 is a block diagram showing the general construction of an example of the IC tester comprising a tester part and a handler connected to the tester part in which the handler has two test stations provided therein which are synchronously operated so that ICs to be tested in the two test stations can be tested at the same time. This IC tester 100 comprises a tester part 1 including a tester proper 1a, a test or tester head 1b and an input part 1c, and a handler 2 connected to the tester part 1.
The tester proper 1a includes an input/output interface circuit (hereinafter referred to as I/O circuit) 3, and a central processing unit (hereinafter referred to as CPU) 4, a read-only memory (hereinafter referred to as ROM) 5 and a random access memory (hereinafter referred to as RAM) 6 all of which are connected to the I/O circuit 3. The test head 1b is separated from the tester proper 1a and is disposed at a first and a second test stations 15a and 15b of the handler 2. The first and second test stations 15a and 15b will be discussed later. The CPU 4 reads out a system program stored in the ROM 5 therefrom to decode and process it, thereby to control the operations of the tester part 1 and the handler 2.
The handler 2 comprises a loader section 16 where ICs to be tested which a user has beforehand loaded on universal trays or customer trays (hereinafter referred to as universal tray) are transferred and reloaded onto a test tray 14 capable of withstanding high/low temperatures, a chamber section for testing ICs under test 13 such as semiconductor memories which have been brought therein as loaded on a test tray 14, and an unloader section 17 where the tested ICs which have been carried on the test tray 14 out of the chamber section subsequently to undergoing a test therein are transferred from the test tray 14 to the universal trays to be reloaded on the latter. The unloader section 17 is generally configured to sort out tested ICs based on the data of the test results and load them on the corresponding universal trays.
The chamber section comprises a constant temperature or thermostatic chamber (soak chamber) 12a for imposing temperature stresses of either a designed high or low temperature on ICs under test 13 loaded on a test tray 14, a first and a second test chambers 12b and 12c for conducting a primary (first) measure and a secondary (second) measure on the ICs under the temperature stress imposed in the constant temperature chamber 12a respectively, and a temperature stress removing chamber (exit chamber) 12d for removing the temperature stress imposed in the constant temperature chamber 12a from the ICs having undergone the measures in the test chambers. The test chambers 12b and 12c are disposed in the constant temperature chamber 12a and contain thereunder the test head 1b of the tester part 1, the two test stations 15a and 15b mounted on the test head 1b being disposed in the corresponding first and second test chambers 12b and 12c. The test stations 15a and 1b serve to apply various testing electrical signals to the ICs electrically contacted with the IC sockets thereof through the test head 1b, respectively, and to receive response signals from the ICs and transmit same to the tester part 1.
The test tray 14 is moved in a circulating manner from and back to the loader section 16 sequentially through the constant temperature chamber 12a, the first test chamber 12b, the second test chamber 12c and the temperature stress removing chamber 12d of the chamber section, and the unloader section 17.
If ICs have had a high temperature applied thereto in the constant temperature chamber 12a, the temperature stress removing chamber 12d cools the ICs with forced air down to the room temperature prior to delivering them out to the unloader section 17. If ICs have had a low temperature of, say, about -30.degree. C. applied thereto in the constant temperature chamber 12a, they are heated with heated air or a heater up to a temperature at which no condensation occurs prior to delivering them out to the unloader section 17.
A test tray 14, loaded with many ICs 13 to be tested in the loader section 16, is conveyed from the loader section 16 to the constant temperature chamber 12a of the chamber section which is equipped with a vertical transport means in the temperature stress giving section therein adapted to support a plurality of (say, ten) test trays 14 in the form of a stack. For example, a test tray newly received from the loader section 16 is supported on the top of the stack while the lowermost test tray is delivered out to the first test chamber 12b.
ICs 13 to be tested are loaded with either a predetermined high or low temperature stress as the associated test tray 14 is moved sequentially from the top to the bottom of the stack by the vertically downward movement of the vertical transport means and during a waiting period until the first test chamber 12b is emptied. In the first test chamber 12b and the second test chamber 12c there are disposed the first test station 15a and the second test station 15b, respectively. The test tray 14 which has been carried one by one out of the temperature giving section of the constant temperature chamber 12a is conveyed at first on the first test station 15a where a predetermined number of ICs out of the ICs under test loaded on the test tray are brought into electrical contact with IC sockets mounted to the first test station 15a to conduct the primary measure (test) on the ICs. Upon completion of the primary measure on all of the ICs placed on one test tray, the test tray 14 is conveyed on the second test station 15b where a predetermined number of ICs out of the ICs under test loaded on the test tray are brought into electrical contact with IC sockets mounted to the second test station 15b to conduct the secondary measure (test) on the ICs. Upon completion of the secondary measure on all of the ICs placed on one test tray, the test tray 14 is conveyed to the temperature stress removing temperature chamber 12d where the tested ICs are relieved of the temperature stress to be restored to the room temperature prior to being delivered to the unloader section 17.
Like the temperature stress giving section of the constant temperature chamber 12a as described above, the temperature stress removing chamber 12d is also equipped with a vertical transport means adapted to support a plurality of (say, ten) test trays 14 stacked one on another. For example, a test tray newly received from the second test station 15b is supported at the bottom of the stack while the uppermost test tray is discharged to the unloader section 17. The tested ICs are relieved of the temperature stress to be restored to the outside temperature (room temperature) as the associated test tray 14 is moved successively from the bottom to the top of the stack by the vertically upward movement of the vertical transport means.
The tested ICs as carried on the test tray 14 are passed to the unloader section 17 where they are sorted out by categories based on the data of the test results and transferred onto and stored in the corresponding universal trays. The test tray 14 emptied in the unloader section 17 is deliver red back to the loader section 16 where it is again loaded with ICs to be tested from the universal tray to repeat the same steps of operation.
The handler 2 further includes an input part 7, an I/O circuit 8, a CPU 9, a ROM 10 and a RAM 11. The I/O circuit 8 is connected to the I/O circuit 3 of the tester part 1, and the CPU 9 reads out a system program stored in the ROM 10 under the control of the CPU 4 to decode and process, thereby to control various parts or elements in the handler 2. The CPU 9 cooperates with the tester part 1.
FIG. 6 shows the corresponding relationship between each of the measurement cycles M in the respective test stations 15a (TS1) and 15b (TS2) and a plurality of test trays #1, #2, . . . , #P in the case that ICs under test loaded on the test trays #1, #2, . . . , #P are measured (or tested) in the first test station (TS1) and the second test station (TS2) respectively. Only in the cases of the first cycle (M=1) and the last cycle (M=P+1), the measurement is carried out only in the first test station (TS1) and the second test station (TS2), respectively, and in other cycles simultaneous measurements (parallel measurements) are effected in both the test stations if there occurs no trouble.
FIG. 7 is a flow-chart for explaining the operation of the conventional IC tester described above with reference to FIG. 5. Now it will be explained in the sequence of steps.
Step SO: the maximum waiting time Tmax required for performing the simultaneous measurements in both the test stations (hereinafter referred to simply as the maximum waiting time Tmax for the simultaneous measurements) is written in the RAM 6 of the tester proper 1a from the input part 1c of the tester part 1.
Step S1: at first the measurement cycle M is set to 1 (M=1).
Step S2: a test tray 14 loaded with plural ICs 13 under test thereon is conveyed onto the first test station 15a (TS1) from the constant temperature chamber 12a.
Step S3: the CPU 9 of the handler 2 checks whether a test can be carried out or not in the first test station 15a, and if it can be carried out (YES), the program proceeds to the next step S4.
Step S4: in the handler 2 a Z-drive (elevator means for moving in the up-and-down direction) for moving the test tray in the up and-down direction is actuated to move the test tray downwardly so that the ICs under test are brought into contact with IC sockets of the first test station 15a as the ICs remain loaded on the test tray.
Step S5: the CPU 4 of the tester part 1 checks whether the preparation of a test in the second test station 15b (TS2) can be completed (can be OK) or not, and if it can be completed (YES), the program proceeds to the next step S7, and if it cannot (NO), the program proceeds to a branched step S6.
Step S6: if the preparation of a test in the second test station 15b cannot be completed, the CPU 4 of the tester part 1 waits on till the preparation of a test in the second test station 15b (TS2) is completed within the limit of the maximum waiting time Tmax. That is, during that the waiting time T required for performing the simultaneous measurements (hereinafter referred to simply as the waiting time T for the simultaneous measurements) is equal to or shorter than Tmax (T.ltoreq.Tmax), the program returns back to the previous step S5, and when the waiting time T for the simultaneous measurements is longer than Tmax (T&gt;Tmax), the program proceeds to next step S7.
Step S7: a measurement is performed in the first test station 15a.
Step S8: after the measurement in step S7 is ended, the Z-drive is actuated to move the test tray in the first station 15a upwardly.
Step S9: the test tray is conveyed from the first test station 15a to the second test station 15b.
Step S10: the measurement cycle M is added by one (+1) and the program goes to the next measurement.
Steps S2' to S9': the similar operations carried out in the second test station 15b in case of M.gtoreq.2 similar to the operations (steps S2 to S9) in the first test station 15a described above. When the operations of the steps S2' to S9' are effected, the operations of the steps S2 to S9 are also performed in the first test station in parallel therewith except the measurement cycle of P+1.
Step S11: if M.gtoreq.2, the program proceeds to the next step S2', and if M&lt;2, the program waits till M=2.
From the above discussion of the operation of the conventional IC tester, it can be understood that except the first measurement cycle of M=1 and the last measurement cycle of M=P+1, the simultaneous measurements (parallel measurements) are carried out in other cycles in both the test stations if there occurs no trouble.
Next, another example of the testers of the type to which the present invention is intended to be applied will be described with reference to FIG. 8.
FIG. 8 is a block diagram showing the general construction of an example of the IC tester comprising a tester part 1 and two handlers 2-1 and 2-2 each connected to the tester part 1 in which the two handlers 2-1 and 2-2 are synchronously operated so that ICs to be tested in the two handlers can be tested at the same time. Since the constructions of the tester part 1 of the IC tester 100 and each of the handlers 2-1, 2-2 may be the same as those of the tester part and the handler (but only one test station is provided therein) shown in FIG. 5, only a tester proper 1a and two test heads 1a1 and 1b2 are shown in the tester part 1a, only an I/O circuit 3 is shown in the tester proper 1a, and only an I/O circuit 8 and a test station 15 are shown in each of the handler.
In the IC tester 100 thus constructed, the two handlers 2-1, 2-2 have no way what to know the status of the operation of the other handler. For this reason, it is not always made possible that the measurements of ICs under test can be performed in the respective test heads 1a1 and 1b2 of the two handlers 2-1 and 2-2 at the same time. For example, if one of the handlers temporarily stops due to occurrence of some trouble, the measurement is done only by the other handler during this temporal stop of the one handler, and hence the simultaneous measurements of ICs cannot be carried out. Recently, the test time duration required for ICs under test tends to be long, and it is indispensable to an increase of production that the simultaneous measurements can be performed.
Heretofore, the synchronization of the two handlers 2-1 and 2-2 are taken by the tester part 1. Before the IC tester 100 is started, an operator inputs the maximum waiting time Tmax for the simultaneous measurements into the tester part 1 in consideration of the test time duration, the index time and the like. In general, the tester part 1 is arranged such that after received a test request signal from one handler, it waits a test request signal from the other handler within the limit of the maximum waiting time Tmax.
If such method is adopted, in such case as one handler can under no circumstances perform a test for a while, that is, in case that the tester part need not wait until the maximum waiting time Tmax for the simultaneous measurements elapses, it must always wait until the maximum waiting time Tmax for the simultaneous measurements elapses because any confirmation of the status of the handlers is not effected. In addition, notwithstanding that the simultaneous measurements are made possible if the tester part can wait for a little longer, there is often the case that the test has been started in the one handler.
As discussed above, in case of a conventional IC tester as shown in FIG. 5 which comprises a tester part and a handler connected to the tester part and having two test stations provided therein, if the maximum waiting time Tmax for the simultaneous measurements set to the tester part is too short, there is often the case that the simultaneous measurements are made possible if the tester part can wait for a little longer, which results in a drawback that the throughput of the IC tester is reduced.
Likewise, in case of a conventional IC tester as shown in FIG. 8 which comprises a tester part and two handlers each connected to the tester part, it has the same disadvantage as that described above, and further has a drawback that even if the tester part need not wait until the maximum waiting time Tmax for the simultaneous measurements elapses (for example, a case that the other handler is under an alarm status and a process for removing this alarm status is being conducted, and the like), it always has to wait until the maximum waiting time Tmax elapses.